Mirae Asset Securities logo

A true full-stack player

LPU order win supports reduced foundry valuation discount

We raise our target price for Samsung Electronics (SEC) to W300,000 (from W275,000). We revised up our operating profit estimates by 8.4% for 1Q26 (W40.6tr; +102% QoQ) and 7.6% for 2026 (W244tr; +459% YoY). We also lifted our 1Q26 ASP growth assumptions for DRAM and NAND by 8.4%p (to +53.8%) and 8.0%p (to +53%), respectively.

At GTC 2026, SEC’s foundry was officially announced as the production partner for the new Groq 3 LPU, with shipments scheduled to begin in 3Q26. This marks SEC’s second major foundry order win from a big tech firm, following last year’s AI6 chip order from Tesla (W23tr). The combination of advanced-node foundry operations (now with big tech customers on board) and memory forms a business model that is unprecedented in the industry, pointing to meaningful valuation re-rating potential.

Despite its advanced node technology, we previously assigned an operating value of roughly W75tr to the firm’s foundry/LSI business, applying a 30% discount to the peer average EV/EBITDA in light of the unit’s sustained losses, relatively low EBITDA, and lack of meaningful non-captive customers. Following the latest order win, however, we reduce the discount to 10%.

Implications of securing production order for Groq 3 LPU

The Groq 3 LPU incorporates 500MB of on-chip SRAM and has a bandwidth of 150TB/s, enabling substantial improvements in inference efficiency vs. Blackwell-based systems (with Nvidia indicating gains of up to 35x under certain conditions). As data transfer costs increasingly exceed compute costs in large-scale AI model processing, the importance of on-chip SRAM-based data reuse is rising rapidly.

For similar reasons, it was reported last week that Amazon Web Services plans to adopt Cerebras’s WSE-3 (featuring 44GB of SRAM). However, SRAM cells are built using six transistors per bit, whereas DRAM uses a simpler structure consisting of one transistor and one capacitor. As a result, SRAM requires more than 10x the area of DRAM. Also, SRAM’s more complex cell structure and greater sensitivity limit the extent of area reduction achievable through node scaling relative to logic devices.

Going forward, broader adoption of SRAM in inference accelerators is likely to drive demand for leading-edge foundry wafer capacity. The latest order from Nvidia validates SEC’s ability to mass-produce data center-grade accelerators incorporating high-density on-chip SRAM. Notably, SEC is virtually the only full-stack player capable of spanning the entire memory hierarchy, from SRAM to SSDs.