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HBM to offset macro concerns

Earnings growth intact despite a stronger won

We raise our target price for Samsung Electronics (SEC) by 8.1% to W400,000 (from W370,000). While we revised up our DRAM ASP growth forecasts by 4.8%p for 2026 and 0.3%p for 2027, we lowered our operating profit estimates by 5.7% and 4.2%, respectively, reflecting a stronger won (USD/KRW rate assumption lowered from 1,553 to 1,400). Meanwhile, with the current quarter entering its final month, our 12-month forward valuation now incorporates earnings through 3Q27 (vs. 2Q27 previously).

We forecast operating profit at W106tr for 3Q26, W118tr for 4Q26, and W536tr for 2027. We project DRAM ASP to continue rising, by 16.5% QoQ in 3Q26, 5.4% QoQ in 4Q26, and 22.6% YoY in 2027. Although price growth for commodity DRAM should moderate in 2027, HBM should continue to drive overall DRAM pricing higher, with bit growth of 57% and ASP growth of 49% (vs. 16% and 20% for commodity DRAM, respectively).

Memory leadership to remain intact amid advances in HBM technology

Launched on Sep. 3, GPT-6 Astra has a 1.05mn-token context window, offers a Fast mode with up to twice the processing speed at twice the standard price, and applies higher pricing to prompts exceeding 272,000 tokens. Because generating each token requires the model weights and the entire KV cache to be read again, longer contexts increase memory bandwidth requirements per token. The higher pricing for faster processing and long-context prompts suggests that memory is a key cost driver.

The Jalapeno ASIC was designed around this bottleneck, with OpenAI emphasizing user latency and energy efficiency rather than throughput per chip. User latency is determined by decoding speed, which in turn depends on memory bandwidth. Among recently introduced ASICs, Jalapeno is the only one to feature HBM4, providing 216GiB of capacity and 15.4TB/s of bandwidth.

Meanwhile, because transitioning to newer HBM generations also increases I/O power consumption, the industry is exploring custom HBM architectures. By fabricating the base die on an advanced logic process, these designs reduce the base die’s circuit footprint and overall size and move the memory controller―which occupies 5?10% of the XPU die―from the XPU to the base die. Nvidia’s NVHBM (unveiled on Aug. 26) adopts a similar architecture and offers up to 30% higher bandwidth and 15% lower power consumption than HBM4E.

SEC has also unveiled zHBM, which eliminates the power consumed by the lateral interconnects used in 2.5D packaging. By stacking DRAM directly on top of the XPU and distributing the I/O connections, zHBM targets a 70% reduction in I/O power consumption and more than 2.3x the bandwidth of HBM5. This would free up approximately 100W for additional GPU compute. As further bandwidth gains increasingly depend on base die fabrication and wafer bonding, memory manufacturers could gain greater control over the value chain.